1. Field of the Invention
The present invention relates to a triode ac switch (triac) and, more particularly, to a triac with a holding voltage that is greater than the dc bias voltages that are on the to-be-protected nodes.
2. Description of the Related Art
A triode ac switch (triac) is a device that provides an open circuit between a first node and a second node when the first-to-second node voltage is positive and less than a trigger voltage. When the first-to-second node voltage rises to be equal to or greater than the trigger voltage, the triac provides a low-resistance current path between the first and second nodes. Further, once the low-resistance current path has been provided, the triac maintains the current path as long as the first-to-second node voltage is positive and equal to or greater than a holding voltage that is lower than the trigger voltage.
The triac, which is a symmetrical device, also provides an open circuit between the second node and the first node when the second-to-first node voltage is positive and less than the trigger voltage. When the second-to-first node voltage rises to be equal to or greater than the trigger voltage, the triac provides a low-resistance current path between the second and first nodes. Further, once the low-resistance current path has been provided, the triac maintains the current path as long as the second-to-first node voltage is positive and equal to or greater than the holding voltage. Thus, the triac provides an identical structure to both the first and second nodes.
As a result of these characteristics, triacs have been used to provide electrostatic discharge (ESD) protection for semiconductor circuits. When used for ESD protection, the first node becomes a first to-be-protected node, and the second node becomes a second to-be-protected node.
The triac operates within an ESD protection window that has a maximum voltage defined by the destructive breakdown level of the to-be-protected nodes, and a minimum voltage (also known as a latch-up voltage) defined by any dc bias that is on the to-be-protected nodes. The trigger voltage of the triac is set to a value that is less than the maximum voltage of the window, while the holding voltage is set to a value that is greater than the minimum voltage of the window.
Thus, when the voltage across the first to-be-protected node and the second to-be-protected node is positive and less than the trigger voltage, the triac provides an open circuit between the first to-be-protected node and the second to-be-protected node. Similarly, when the voltage across the second to-be-protected node and the first to-be-protected node is positive and less than the trigger voltage, the triac also provides an open circuit between the second to-be-protected node and the first to-be-protected node.
However, when the first to-be-protected node receives a voltage spike that equals or exceeds the trigger voltage, such as when an ungrounded human-body contact occurs, the triac provides a low-resistance current path from the first to-be-protected node to the second to-be-protected node. Similarly, when the second to-be-protected node receives a voltage spike that equals or exceeds the trigger voltage, the triac provides a low-resistance current path from the second to-be-protected node to the first to-be-protected node.
In addition, once the ESD event has passed and the voltage on the first to-be-protected node falls below the holding voltage, the triac again provides an open circuit between the first to-be-protected node and the output node. Similarly, after the ESD event has passed and the voltage on the second to-be-protected node falls below the holding voltage, the triac again provides an open circuit between the second to-be-protected node and the first to-be-protected node.
FIG. 1 shows a cross-sectional diagram that illustrates a conventional triac 100. As shown in FIG. 1, triac 100 has spaced apart n-wells 112 and 114 which are formed in a p-type material 110, such as a well or a substrate. In addition, triac 100 has a n+ region 116 and a p+ region 118 which are formed in n-well 112, and a n+ region 120 which is formed in p-type material 110 and n-well 112. N+ and p+ regions 116 and 118, in turn, are both connected to a first to-be-protected node 122.
As further shown in FIG. 1, triac 100 also has a n+ region 124 and a p+ region 126 which are formed in n-well 114, and a n+ region 128 which is formed in p-type material 110 and n-well 114. N+ and p+ regions 124 and 126, in turn, are both connected to a second to-be-protected node 130.
Triac 100 further has a channel region 132 that is defined between n+ region 120 and n+ region 128. In addition, triac 100 has a gate oxide layer 134 that is formed on material 110 over channel region 132, and a gate 136 that is formed on gate oxide layer 134. N+ (drain and source) regions 120 and 128, gate oxide layer 134, and gate 136 define a NMOS transistor 140 which is typically formed to be identical to the to-be-protected MOS transistors in the circuit.
In operation, when the voltage on the drain of a conventional NMOS transistor spikes up, the drain-to-substrate junction of the NMOS transistor breaks down, for example, at 7 volts, while the gate oxide layer that isolates the gate from the drain destructively breaks down at, for example, 10-15 volts.
When a voltage across nodes 122 and 130 is positive and less than a trigger voltage, the voltage reverse biases the junction between n+ (drain) region 120/n-well 112 and p-type material 110, and forward-biases the junction between n+ (source) region 128/n-well 114 and p-type material 110. The reverse-biased junction, in turn, blocks current from flowing from node 122 to node 130.
On the other hand, when the voltage across nodes 122 and 130 is equal to or greater than the trigger voltage, the reverse-biased junction breaks down due to avalanche multiplication. Since NMOS transistor 140 is formed to be identical to the to-be-protected MOS transistors, the junction between n+ region 120 and p-type material 110 breaks down at the same time that the to-be-protected MOS transistors experience junction break down.
Since junction break down occurs before the MOS transistors experience destructive gate oxide break down, triac 100 turns on before destructive gate oxide breakdown occurs, thereby protecting the MOS transistors. Thus, the junction break down voltage, which is less than the voltage level that causes destructive gate oxide break down, functions as the trigger voltage.
The breakdown of the junction due to avalanche multiplication causes a large number of holes to be injected into p-type material 110, and a large number of electrons to be injected into n-well 112. The holes injected into material 110 turn on a npn transistor that utilizes n+ region 128 as an emitter, p-type material 110 as a base, and n-well 112 as a collector.
When the npn transistor turns on, n+ (emitter) region 128 injects electrons into (base) material 110. Most of the injected electrons diffuse through (base) material 110 and are swept from (base) material 110 into (collector) n-well 112 by the electric field that extends across the reverse-biased junction. The electrons in (collector) n-well 112 are then collected by n+ region 116.
A small number of the electrons injected into (base) material 110 recombine with holes in (base) material 110 and are lost. The holes lost to recombination with the injected electrons are replaced by holes injected into (base) material 110 by the broken-down reverse-biased junction and, as described below, by the collector current of a pnp transistor.
The electrons that are injected and swept into n-well 112 also decrease the potential of n-well 112 in the region that lies adjacent to p+ region 118, and eventually forward bias the junction between p+ region 118 and n-well 112. When the decreased potential forward biases the junction between p+ region 118 and n-well 112, a pnp transistor that utilizes p+ region 118 as an emitter, n-well 112 as a base, and material 110 as a collector turns on.
When turned on, p+ (emitter) region 118 injects holes into (base) n-well 112. Most of the injected holes diffuse through (base) n-well 112 and are swept from (base) n-well 112 into (collector) material 110 by the electric field that extends across the reverse-biased junction. The holes in (collector) material 110 flow into the forward-biased junction between p-type material 110 and n+ region 128/n-well 114, and are then collected by p+ region 126.
A small number of the holes injected into (base) n-well 112 recombine with electrons in (base) n-well 112 and are lost. The electrons lost to recombination with the injected holes are replaced by electrons flowing into n-well 112 as a result of the broken-down reverse-biased junction, and n-well 112 being the collector of the npn transistor. Thus, a small part of the npn collector current forms the base current of the pnp transistor.
Similarly, as noted above, the holes swept into (collector) material 110 also provide the base current holes necessary to compensate for the holes lost to recombination with the diffusing electrons injected by n+ (emitter) region 128. As a result, a small part of the pnp collector current forms the base current of the npn transistor.
Thus, n+ region 128 injects electrons that provide both the electrons for the collector current of the npn transistor as well as the electrons for the base current of the pnp transistor. At the same time, p+ region 118 injects holes that provide both the holes for the collector current of the pnp transistor as well as the holes for the base current of the npn transistor.
When a voltage spike occurs on the second to-be-protected node rather than the first to-be-protected node, triac 100 operates the same, only in reverse. Thus, when a voltage across nodes 128 and 122 is positive and less than a trigger voltage, the voltage reverse biases the junction between n+ region 128/n-well 114 and p-type material 110, and forward-biases the junction between n+ region 120/n-well 112 and p-type material 110. The reverse-biased junction, in turn, blocks current from flowing from node 128 to node 122.
On the other hand, when the voltage across nodes 128 and 122 is equal to or greater than the trigger voltage, the reverse-biased junction breaks down due to avalanche multiplication. The breakdown causes a large number of holes to be injected into p-type material 110, and a large number of electrons to be injected into n-well 114.
The injected holes turn on a npn transistor that utilizes n+ region 120 as an emitter, p-type material 110 as a base, and n-well 114 as a collector. When the npn transistor turns on, n+ (emitter) region 120 injects electrons into (base) material 110. Most of the injected electrons diffuse through (base) material 110 and are swept from (base) material 110 into (collector) n-well 114 by the electric field that extends across the reverse-biased junction. The electrons in (collector) n-well 114 are then collected by n+ region 124.
A small number of the electrons injected into (base) material 110 recombine with holes in (base) material 110 and are lost. The holes lost to recombination with the injected electrons are replaced by holes injected into (base) material 110 by the broken-down reverse-biased junction and the collector current of a pnp transistor.
The electrons that are injected and swept into n-well 114 also decrease the potential of n-well 114 in the region that lies adjacent to p+ region 126, and eventually forward bias the junction between p+ region 126 and n-well 114. When the decreased potential forward biases the junction between p+ region 126 and n-well 114, a pnp transistor that utilizes p+ region 126 as an emitter, n-well 114 as a base, and p-type material 110 as a collector turns on.
When turned on, p+ (emitter) region 126 injects holes into (base) n-well 114. Most of the injected holes diffuse through (base) n-well 114 and are swept from (base) n-well 114 into (collector) material 110 by the electric field that extends across the reverse-biased junction. The holes in (collector) material 110 flow into the forward-biased junction between material 110 and n-well 112, and are then collected by p+ region 118.
A small number of the holes injected into (base) n-well 114 recombine with electrons in (base) n-well 114 and are lost. The electrons lost to recombination with the injected holes are replaced by electrons flowing into n-well 114 as a result of the broken-down reverse-biased junction, and n-well 114 being the collector of the npn transistor. Thus, a small part of the npn collector current forms the base current of the pnp transistor.
Similarly, the holes swept into (collector) material 110 also provide the base current holes necessary to compensate for the holes lost to recombination with the diffusing electrons injected by n+ (emitter) region 120. As a result, a small part of the pnp collector current forms the base current of the npn transistor.
Thus, n+ region 120 injects electrons that provide both the electrons for the collector current of the npn transistor as well as the electrons for the base current of the pnp transistor. At the same time, p+ region 126 injects holes that provide both the holes for the collector current of the pnp transistor as well as the holes for the base current of the npn transistor.
Some of the advantages of triac 100 over other ESD protection devices, such as a grounded-gate MOS transistor, are the double protection and double injection provided by triac 100. For double protection, triac 100 provides ESD protection regardless of whether the ESD event takes place on first node 122 or second node 130. For double injection, n+ region 128 injects electrons and p+ region 118 injects holes when the ESD event takes place on first node 122, and n+ region 120 injects electrons and p+ region 126 injects holes when the ESD event takes place on second node 130.
With double injection, triac 100 provides current densities (after snapback) that are about ten times greater than the densities provided by a grounded-gate MOS device, thus increasing the ESD protection capability. (Protection capability can be defined as the required contact width of the structure required to protect from a given ESD pulse amplitude, or the maximum protected ESD pulse amplitude for a given contact width.)
One of the disadvantages of triac 100, however, is that triac 100 suffers from a holding voltage that is often less than the minimum (or latch-up) voltage of the ESD protection window. As a result, triacs are unattractive candidates for providing ESD protection to power supply pins.
When the minimum (or latch-up) voltage of the ESD protection window is equal to a dc bias, such as the power supply voltage, and the holding voltage is less than the minimum voltage, triac 100 can not turn off (thus latching up) after the ESD event has passed. Thus, power must be cycled after the ESD event.
For example, assume that node 122 is a power supply pin at 3.3 volts, node 130 is a ground pin, the junction breakdown voltages of the to-be-protected MOS transistors are 7.0 volts, and the holding voltage is 1.8 volts. In this example, triac 100 is turned off under normal operating conditions when the voltage on node 122 is 3.3 volts. When the voltage on node 122 spikes up to a value equal to or greater than the trigger voltage (7 volts in this example), triac 100 turns on, thereby protecting the MOS devices that receive power from node 122.
However, once the ESD event has passed, it takes only 1.8 volts on node 122 to keep triac 100 in this example turned on. Since the normal operating voltage on node 122 is 3.3 volts, triac 100 remains turned on (is latched up) after the ESD event has passed. Thus, to provide ESD protection to lines with a dc bias, such as power supply lines, via a triac, there is a need for a triac with a holding voltage that is greater than the dc bias.
The present invention provides a low-voltage triggering silicon-controlled rectifier (LVTSCR) that increases the value of the holding voltage by inserting a voltage drop circuit between a to-be-protected node with a dc bias, such as a power supply node, and the emitter of the pnp transistor of the LVTSCR.
A low-voltage triggering silicon-controlled rectifier (LVTSCR) in accordance with the present invention is formed in a semiconductor material of a first conductivity type, and includes a well of a second conductivity type that is formed in the semiconductor material. The LVTSCR also includes a first region of the second conductivity type that is formed in the well, and a second region of the first conductivity type that is formed in the well. The first region is connected to a first node.
The LVTSCR further includes a third region of the second conductivity type that is formed in the semiconductor material, and a fourth region of the first conductivity type that is formed in the semiconductor material. The third and fourth regions are connected to a second node. The LVTSCR additionally includes a fifth region of the second conductivity type that is formed in the semiconductor material, and a voltage drop circuit that is connected between the second region and the first node.
The present invention also includes a method for operating the LVTSCR that includes the steps of placing a first voltage on the first region, and placing a second voltage on the second region where the first and second voltages are different. In addition, the method includes the step of placing a third voltage on the third and fourth regions.